17 radhard msi logic UT54ACS10/ut54acts10 radiation-hardened triple 3-input nand gates features ? radiation-hardened cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip - 14-lead flatpack description the UT54ACS10 and the ut54acts10 are triple three-input nand gates. the circuits perform the boolean functions y = a b c or y = a + b + c in positive logic. the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram inputs output a b c y h h h l l x x h x l x h x x l h y1 (12) (6) y2 y3 (8) (1) a1 (2) b1 (13) c1 (3) a2 (4) b2 (5) c2 (9) a3 (10) b3 note: . 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. (11) c3 1 2 3 4 5 7 6 14 13 12 11 10 8 9 a1 b1 a2 b2 c2 y2 v ss v dd c1 y1 c3 b3 a3 y3 v dd c1 y1 c3 b3 a3 y3 a1 b1 a2 b2 c2 y2 v ss 1 2 3 4 5 7 6 14 13 12 11 10 8 9 y1 a1 b1 c1 y2 a2 b2 c2 y3 a3 b3 c3
radhard msi logic 18 UT54ACS10/ut54acts10 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute m aximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
19 radhard msi logic UT54ACS10/ut54acts10 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
radhard msi logic 20 UT54ACS10/ut54acts10 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t phl input to yn 1 16 ns t plh input to yn 1 12 ns
|
